? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice 1 cat24fc17 16-kb i 2 c serial eeprom doc. no. 1077, rev. f * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. pin configuration block diagram pin functions pin name function nc no connect sda serial data/address scl serial clock wp write protect v cc 2.5 v to 5.5 v power supply v ss ground dip package (p, l, gl) tssop package (u, y, gy) soic package (j, w, gw) features 400 khz (2.5 v) i 2 c bus compatible 2.5 to 5.5 volt operation low power cmos technology 16-byte page write buffer industrial and extended temperature ranges self-timed write cycle with auto-clear 1,000,000 program/erase cycles 100 year data retention 8-pin dip, 8-pin soic, 8-pin tssop, 8-pin msop and tdfn packages - green package option available 256 x 8 memory organization hardware write protect - top 1/2 array protected when wp at v ih description the cat24fc17 is a 16-kb serial cmos eeprom internally organized as 2048 words of 8 bits each. catalysts advanced cmos technology substantially reduces device power requirements. the cat24fc17 features a 16-byte page write buffer. the device operates via the i 2 c bus serial interface has a special write protection feature and is available in 8-pin dip, soic, tssop, msop and tdfn packages. d out ack sense amps shift registers control logic word address buffers start/stop logic state counters e 2 prom v cc external load column decoders xdec data in storage high voltage/ timing control v ss scl sda wp tdfn package (rd4, zd4, gd4) 8 7 6 5 1 2 3 4 nc nc nc v s s v cc wp scl sda 1 2 3 4 8 7 6 5 nc nc nc v ss v cc wp scl sda msop package (r, z, gz) v cc wp scl sda 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 v cc wp scl sda nc nc nc v ss nc nc nc v ss 8 7 6 5 v cc wp scl sda 1 2 3 4 nc nc nc v ss discontinued part
cat24fc17 2 doc. no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice capacitance t a = 25 c, f = 400 khz, v cc = 5 v symbol test conditions min typ max units c i/o (3) input/output capacitance (sda) v i/o = 0 v 8 pf c in (3) input capacitance (other pins) v in = 0 v 6 pf reliability characteristics (3) symbol parameter min typ max units n end endurance 1,000,000 cycles/byte t dr data retention 100 years v zap esd susceptibility 4000 volts i lth (4) latch-up 100 ma absolute maximum ratings* temperature under bias C 55 c to +125 c storage temperature ....................... C 65 c to +150 c voltage on any pin with respect to ground (1) ............ C 2.0 v to v cc + 2.0 v v cc with respect to ground ............. C 2.0 v to +7.0 v package power dissipation capability (t a = 25 c) .................................. 1.0 w note: (1) the minimum dc input voltage is C 0.5 v. during transitions, inputs may undershoot to C 2.0 v for periods of less than 20 ns. maximum dc voltage on output pins is v cc + 0.5 v, which may overshoot to v cc + 2.0 v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) these parameters are tested initially and after a design or process change that affects the parameter according tp appropria te aec-q100 and jedec test methods. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1.0 v to v cc + 1.0 v. (5) maximum standby current (i sb ) = 10 a for the extended automotive temperature range. d.c. operating characteristics v cc = 2.5 v to 5.5 v, unless otherwise specified. symbol parameter test conditions min typ max units i cc power supply current (read) f scl = 400 khz 1 ma i cc power supply current (write) f scl = 400 khz 3 ma i sb (5) standby current (v cc = 5.0 v) v in = gnd or v cc 1 a i li input leakage current v in = gnd to v cc 1 a i lo output leakage current v out = gnd to v cc 1 a v il input low voltage C 1v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol output low voltage (v cc = 3.0 v) i ol = 3 ma 0.4 v lead soldering temperature (10 seconds) ...... 300 c output short circuit current (2) ....................... 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. discontinued part
cat24fc17 3 doc no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice write cycle limits symbol parameter min typ max units t wr write cycle time 5 ms a.c. characteristics v cc = 2.5 v to 5.5 v, unless otherwise specified. read & write cycle limits symbol parameter 2.5 v - 5.5 v min max units f scl clock frequenc 400 khz t i (1) noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out and ack out 900 ns t buf (1) time the bus must be free before a new transmission 1300 ns can start t hd:sta start condition hold time 600 ns t low clock low period 1300 ns t high clock high period 600 ns t su:sta start condition setup time 600 ns (for a repeated start condition) t hd:dat data in hold time 0 ns t su:dat data in setup time 100 ns t r (1) sda and scl rise time 300 ns t f (1) sda and scl fall time 300 ns t su:sto stop condition setup time 600 ns t dh data out hold time 100 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. power-up timing (1)(2) symbol parameter min typ max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. discontinued part
cat24fc17 4 doc. no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice functional description the cat24fc17 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. data transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24fc17 operates as a slave device. both the master and slave devices can operate as either transmitter or receiver, but the master device controls which mode is activated. start bit sda stop bit scl figure 3. start/stop timing figure 2. write cycle timing t wr stop condition start condition address ack 8th bit byte n scl sda t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 1. bus timing pin descriptions scl: serial clock the cat24fc17 serial clock input pin is used to clock all data transfers into or out of the device. this is an input pin. sda: serial data/address the cat24fc17 bidirectional serial data/address pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. wp: write protect this input, when tied to gnd, allows write operations to the entire memory. when this pin is tied to v cc , the upper half of the memory array is write protected. when left floating or tied to v ss, normal read/write operations are allowed. discontinued part
cat24fc17 5 doc no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice i 2 c bus protocol the following defines the features of the i 2 c bus proto- col: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24fc17 monitor the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 1010 for the cat24fc17 (see fig. 5). the next three significant bits (a10, a9, a8) are the memory array address bits. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat24fc17 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat24fc17 then performs a read or a write operation depending on the state of the r/ w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledg- ing device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat24fc17 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each byte. when the cat24fc17 begins a read mode, it trans- mits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this ac- knowledge, the cat24fc17 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. figure 4. acknowledge timing figure 5. slave address bits acknowledge 1 start scl from master 89 data output from transmitter data output from receiver 1 device address 0 1 0 a10 a9 a8 r/w normal read and write discontinued part
cat24fc17 6 doc. no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the cat24fc17. after receiving another acknowledge from the slave, the master device transmits the data byte to be written into the addressed memory location. the cat24fc17 acknowledges once more and the master generates the stop condition, at which time the device begins its internal programming to nonvolatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the cat24fc17 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial word is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been transmitted the cat24fc17 will respond with an acknowledge, and internally increment the low order address bits by one. the high order bits remain unchanged. if the master transmits more than 16 bytes prior to sending the stop condition, the address counter wraps around , and previously transmitted data will be overwritten. once all 16 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point all received data is written to the cat24fc17 in a single write cycle. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write operation, the cat24fc17 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the cat24fc17 is still busy with the write operation, no ack will be returned. if the cat24fc17 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection the cat24fc17 is designed with a hardware protect pin that enables the user to protect the upper half of the memory. the hardware protection feature of the cat24fc17 is designed into the part to provide added flexibility to the design engineers. the write protection feature of cat24fc17 allows the user to protect against inadvertent programming of memory locations 400 h to 7 ffh. if the wp pin is tied to vcc, the upper half of the memory array is protected and becomes read only. if the wp pin is left floating or tied to vss, the device can be written into. figure 7. page write timing byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t bus activity: master sda line data n+p byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address note: in this example n = xxxx 0000(b); x = 1 or 0 * figure 6. byte write timing discontinued part
cat24fc17 7 doc no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice read operations the read operation for the cat24fc17 is initiated in the same manner as the write operation with the one exception that the r/ w bit is set to a one. three different read operations are possible: immediate address read, selective read and sequential read. immediate address read the cat24fc17 s address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n + 1. if n = 2047 for 24fc17, then the counter will wrap around to address 0 and continue to clock out data. after the cat24fc17 receives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the cat24fc17 acknowledge the word address, the master device resends the start condition and the slave address, this time with the r/ w bit set to one. the cat24fc17 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat24fc17 sends the initial 8-bit data requested, the master will respond with an acknowledge which tells the device it requires more data. the cat24fc17 will continue to output a byte for each acknowledge sent by the master. the operation will terminate operation when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from the cat24fc17 is outputted sequentially with data from address n followed by data from address n + 1. the read operation address counter increments all of the cat24fc17 address bits so that the entire memory array can be read during one operation. if more than the 2047 bytes are read out, the counter will wrap around and continue to clock out data bytes. figure 8. immediate address read timing scl 8 9 sda 8th bit stop no ack data out slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t discontinued part
cat24fc17 8 doc. no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice figure 9. selective read timing figure 10. sequential read timing slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address discontinued part
cat24fc17 9 doc no. 1077, rev. f ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice ordering information notes: (1) the device used in the above example is a 24fc17ji-te13 rev-f (soic, industrial temperature, 2.5 volt to 5.5 volt operating voltage, tape & reel). prefix device # suffix 24fc17 j i product number package cat temperature range i = indust ri optional company id p: pdip j: soic, jedec r: msop u: tssop rd4: tdfn l: pdip (lead-free, halogen-free) w: soic, jedec (lead-free, halogen-free) y: tssop (lead-free, halogen-free) z: msop (lead-free, halogen-free) zd4: tdfn (lead-free, halogen-free) gl: pdip (lead-free, halogen-free, nipdau lead plating) gw: soic, jedec (lead-free, halogen-free, nipdau lead plating) gy: tssop (lead-free, halogen-free, nipdau lead plating) gz: msop (lead-free, halogen-free, nipdau lead plating) gd4: tdfn (lead-free, halogen-free, nipdau lead plating) te13 tape & reel rev-f die revision discontinued part
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.caalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 minipot catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 1077 revison: f issue date: 08/02/05 3/+ % ! & 4 6 4 % ! " " & 3 0 / 8 1 / 1 1a e u s s i l a i t i n i 4 0 / 5 1 / 5 0b s c i t s i r e t c a r a h c g n i t a r e p o . c . d s t i m i l e l c y c e t i r w n o i t a m r o f n i g n i r e d r o e t a d p u y r o t s i h n o i s i v e r e t a d p u r e b m u n v e r e t a d p u 4 0 / 7 0 / 6 0c s t i m i l e l c y c e t i r w e t a d p u 4 0 / 7 2 / 7d 2 e g a p n o s e t o n d e t a d p u 5 0 / 4 2 / 3 0e s e r u t a e f e t a d p u n o i t p i r c s e d e t a d p u n o i t c n u f n i p e t a d p u s c i t s i r e t c a r a h c y t i l i b a i l e r e t a d p u s c i t s i r e t c a r a h c g n i t a r e p o . c . d e t a d p u s c i t s i r e t c a r a h c . c . a e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u 5 0 / 2 0 / 8 0f n o i t c n u f n i p e t a d p u n o i t a m r o f n i g n i r e d r o e t a d p u discontinued part
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